A 60ns CMOS DSP with on-chip instruction cache
C. Caren, B. Benjamin, James R. Boddie, M.L. Fuccio, Renato N. Gadenz, W. Patrick Hays, L. McMillan, J. Henry, L.E. Bays, Aarti Gupta, J. Klinikowski, G. Komoriya, L. Rigge, D. Willenbecher, Kaichuen Wong · 1987
A 16b fixed point programmable DSP with a 60ns instruction cycle time will be discussed. Fabricated in twin tub, 1μm CMOS, the chip includes 2K words of ROM, 512 words of RAM and an instruction cache for fast vector operations.