An efficient VLSI implementation of vector-radix 2-D DCT using mesh-connected 2-D array
Kyung-Wook Shin, Heung-Woo Jeon, Yong-Seum Kang · 2002
This paper describes an efficient array algorithm for parallel computation of vector-radix two-dimensional (2-D) discrete cosine transform (VR-DCT), and its VLSI implementation. By mapping the 2-D VR-DCT onto a 2-D array of processing elements (PEs), the DCT is efficiently computed with high concurrency and local data exchanges between PEs. The proposed array algorithm features architectural modularity, regularity and locality, so that it is very suitable for VLSI realization. Also, no transposition memory is required. It has the time complexity of O(N+N/sub NZD//spl middot/log/sub 2/N) for (N/spl times/N) 2-D DCT, where N/sub NZD/ is the number of non-zero digits in the canonic-signed digit (CSD) representation of DCT kernel. Based on the proposed array algorithm, an array processor for (8/spl times/8) 2-D DCT is designed using 1.5 /spl mu/m double metal CMOS technology. From simulation results, it is estimated that (8/spl times/8) 2-D DCT (with N/sub NZD/=4) can be computed in about 0.88 /spl mu/sec at 50 MHz clock frequency, resulting in the throughput rate of about 72 Mega pixels/sec.>