Efficient systolic array for singular value and eigenvalue decomposition
A. Ahmedsaid, Abbes Amira, Ahmed Bouridane · 2006
This paper presents an efficient systolic array for the computation of the singular value decomposition (SVD) and the symmetric eigenvalue decomposition (EVD). The proposed architecture is three times more efficient and faster than the Brent, Luk, Van Loan (BLV) SVD/EVD systolic array. The architecture has been implemented efficiently on FPGA using a high level language for hardware design "Handel-C".