Design and analysis of an asynchronous checkpoint-based redundant multithreading architecture
Jie Yin, Jianhui Jiang · World Automation Congress · 2012
Redundant multithreading (RMT) architectures detect errors by comparing the result of each instruction of the master and slave threads, which leads to large overhead caused by comparison and communication. To address this problem, several enhanced architectures were proposed. However, some of them have lower performance and lower error detection coverage. This paper presents an asynchronous checkpoint-based redundant multithreading (AC-RMT) architecture, in which two contexts saving rooms are set aside for each thread, one for detecting faults, the other for saving the last checkpoint used for fault restoration. In AC-RMT, enhanced load value queue (LVQ) and store buffer (STB) are setup for committing store results in time. It can avoid the waiting of master threads at checkpoints, so resources can be released timely. Experiments show that AC-RMT can reduce more number of comparisons than that of SRTR and boost performance efficiently with lower overhead than that of register value queue free recovery scheme (RVQ_F).