A coprocessor with supercomputer capabilities for personal computers
Warren Marwood, AP Clarke · 2003
The architecture of a matrix product coprocessor with supercomputer capabilities is described. It consists of a three-chip set requiring two custom VLSI chip designs, and a 50-ns memory subsystem and associated software drivers. One chip design implements a reconfigurable systolic array of simple processing elements, and the other provides both a generic interface to a host processor and schedules data and control sequences to and from the systolic array. Some indication is given of the use of the machine for the computation of Fourier transforms and the inversion of matrices. The expected performance for these tasks compares favorably with reported performances of supercomputers. Systems performance is 140 MFLOPS (million floating-point operations per second). The coprocessor takes the form of a module implementable on a single IBM/PC plug-in board.>