The architecture of the LR33000: a MIPS compatible RISC processor for embedded control applications
B. Caulk, S. Desai, M. Gavrielov, G. Harper, D. Jones, M. Kwong, M. Murzello, T. Oke, J. Patel, R. Peck, J. Wei, Ran Yang · 2002
RISC processors have been widely accepted in the performance driven segments of the reprogrammable computer market such as workstations and file servers. However, these chips, despite their high levels of performance, do not adequately address embedded control applications. A description is given for the macro- and micro-architecture of the LR 33000, a single chip, 50 MHz, RISC processor, which was designed and optimized for embedded control applications while retaining both software compatibility with the MIPS-1 instruction set and a high level of performance. The optimization for embedded control applications was done by focusing on the following goals: minimizing the overall system cost by increasing the level of integration, simplifying the system design, and reducing the power consumption.>