An area-efficient architecture for Reed-Solomon decoder using the inversionless decomposed Euclidean algorithm
Hsie-Chia Chang, Chen‐Yi Lee · 2002
We propose a new area-efficient architecture to implement the Euclidean algorithm, which is frequently used in BCH and Reed-Solomon decoders. For Reed-Solomon decoders, our architecture can be applied to the correction of errors as well as erasures. An inversionless decomposed Euclidean algorithm is adopted which not only eliminates the finite-field inverter (FFI) but also introduces an efficient computation procedure as compared with previous researches. Though the decomposed algorithm takes more cycles to finish, the overall decoding speed is maintained. We derive the conditions of the code size to which the architecture can be applied, and show that many important applications in communications and storage systems can all benefit from our proposed architecture.