Bipolar, CMOS and BiCMOS circuit technologies examined for testability
E. Kofi Vida-Torku, William R. Reohr, J.A. Monzel, P. Nigh · 2002
A circuit-level testability comparison of bipolar, CMOS and BiCMOS logic technologies is presented. Process defects from each technology are examined to determine the fault models that best detect these defects. Commonalities and differences of fault models among the circuit types are described. The test cost required to obtain the same quality in each technology is described. It is shown that bipolar circuits can be effectively tested by the stuck fault model. To achieve high test coverage in CMOS circuits, stuck fault and current testing should be applied. Current testing can be effective in CMOS if the appropriate patterns are generated. BiCMOS requires delay testing. While current measurement could detect a few defects, it is not enough to replace delay test in BiCMOS. Delay testing may not detect all defects even if test vectors are available. Furthermore, it is expensive in test generation and test hardware cost. This suggests that design-for-test features may even be more important for BiCMOS circuits than for CMOS or bipolar circuits.>