Virtually addressed caches for multiprogramming and multiprocessing environments
Verna Elizabeth Knapp · 1985
Virtually addressed caches offer advantages of improved performance and simplicity of design over real addressed caches. They have not been generally used because their implementation presents some difficulties. A technique was devised to allow the use of virtually addressed cache by multiple processes sharing global memory without cache coherency problems. When the question of how to best combine I/O subsystems with virtually addressed cache using that technique was raised, several more problems were discovered. These included the MMU coherency problem and the question of whether the MMU should be associated with the processor or with main memory. The advantages and disadvantages of a large number of locations of processors, caches, buses, MMUs, and main memories were discussed. Associating the MMU(s) with main memory rather than with the cache or the processor has a number of advantages. These advantages include a solution to the MMU coherency problem, better performance, virtual addresses for I/O which yields uniform addresses for all references, and simplicity of design. An implementation of the ideas developed in this dissertation is proposed. The system to be implemented is a multiprocessor workstation using shared global memory for multiprocessing and multiprogramming tasks. Operating system and system software issues are discussed. In the uniprocessor case, the expected performance gain due to using virtually addressed cache is significant, primarily because it allows non-paged address translation units to be used. Comparisons were made between real address cache architectures and virtual address cache architectures. In the multiprocessor case, there is also a gain in performance for all of the reasons which apply with uniprocessors, plus a reduction in bus contention. There is also a considerable reduction in the complexity of the system. All of the processors, including I/O processors, can be treated in a uniform fashion with respect to the protocol for memory access. Each processor deals with virtual addresses only. Translation of virtual addresses is defered until a main memory reference occurs. The main memory translates the virual address to a real address, maintains cache coherency between the various processors, detects page faults, and transfers data.