RTL/ISS co-modeling methodology for embedded processor using SystemC
Yoichi Yuyama, Masao Aramoto, Kazutoshi Kobayashi, Hidetoshi Onodera · 2004
We propose ISS/RTL co-modeling methodology by describing both in common source file using SystemC. Our method enables rapid and easy generation/verification of RTL/ISS of customizable processor. We apply this method to processor "MiU-Processor". As a result coded-sharing ratio is 67%. For adding new instruction, we add only 12 lines to RTL/ISS shared apart. Our ISS generation method is very effective for multi customizable SoC.