Easily testable PLA-based FSMS
M.J. Avedillo, José María Quintana, J.L. Huertas · 1993 IEEE International Symposium on Circuits and Systems · 2002
A new hardware scheme for easily testable programmable logic array (PLA)-based finite state machines is proposed. With the authors' scheme, all combinationally irredundant crosspoint faults in the PLA logic implementation are testable. Test generation is easily accomplished because short systematic initialization sequences exist for each internal state in the machine and unit length distinguishing sequences. The scheme is outlined. It consists of the addition of some state transitions and their outputs to the state transition graph (STG) of the machine. A test generation procedure which does not require fault simulation or the manipulation of the STG of the machine is described.>