Standard Cell Design for Testable Self-Timed Systems
O. Salomon, Heinrich Klar · European Solid-State Circuits Conference · 1993
A standard cell library in DCVS-logic for the automatic design of testable self-timed systems has been designed in 1.0?m CMOS technology. Two standard cell designs using this library have been implemented on one test chip. A 4*4 bit pipelined field multiplier with scan-path (0.78mm2, 85 MHz simulated) and a 4*4 bit serial/parallel multiplier (0.51 mm2, 110 MHz simulated) show the usability of this library. DCVSL-gates have complementary input and output signals determining the area of the cells, and their intercell wiring cause a considerable channel area. Therefore, complex standard cells are preferred because they cause smaller chip area and operate faster than basic standard cells. A DCVSL-gate with integrated storage element and the handshake element can be easily extended to scan-path elements for the system's test. The scan-path elements do not contribute any gate delays during the computation mode.