Bridging Faults in CMOS: Possibilities of Current Testing
Rosa M. Rodriguez, J. Segura, Victor H. Champac, Joan Figueras, Javier Rubio · European Solid-State Circuits Conference · 1990
Bridging faults have been shown to be a major failure mode in CMOS IC's [SHE85]. A model that takes into account the different resistance values of the bridge is presented. This model is used to estimate the I DDQ range of values to evaluate the possibility of current testing of this fault [NIG90]. A simple circuit is used as an example. This methodology is demonstrated to provide a greater domain of detectability of bridging faults than the classical approaches.