Systolic implementation for deconvolution iterative algorithm
J. Navarro-Guerrero, Vicente Casares‐Giner · 2005
Systolic architectures implement regular algorithms in hardware, in order to obtain high computational throughput. In this paper we provide a modular architecture for a deconvolution iterative algorithm. The basic module is a systolic array which implement one iteration of the algorithm recently proposed in [1]. The algorithm is a generalization of the method to invert non singular polynomial transfer function, previously published in [2]. The basic systolic module can be repeatedly concatenated in such a way that can be used in real time applications.