Arbitration latency analysis of the shared channel architecture for high performance multi-master SoC
Jisuhn Suh, Hoi‐Jun Yoo · Proceedings of 2004 IEEE Asia-Pacific Conference on Advanced System Integrated Circuits · 2004
We propose new analysis method to estimate the traffic performance of communication channel for system-on-chip (SoC). We define the channel utilization ratio, and we analyze the traffic performance of multi-master system-onchip on shared channel architecture by measure of the arbitration latency. This method is efficient to evaluate the traffic characteristics of the shared channel architecture. And this results offer the methods to optimize the parameter of the components to achieve high performance channel. To verify the efficiency of this method, we experiment the latency of single shared channel architecture by various conditions of components composing SoC. We simulated the effect of number of masters and 2 types of arbitration algorithm by using defined channel utilization ratio. In this analysis, it is found that the arbitration latency increases with the number of masters and channel utilization ratio. The arbitration algorithm affects the arbitration latency according to the number of masters. The throughput of data transaction is proportional to channel utilization ratio.