Performance evaluation of the memory hierarchy of a desktop PC using commodity chips with specific traces
A. Pavlov, Jean-Luc Béchennec, Daniel Etiemble · 2002
We present a methodology to evaluate performance of the memory hierarchy of PC microcomputers. This methodology is based on synthetic bus traces which allow simulation of the memory hierarchy without having to build a model of the microprocessor. As a result, the simulation is orders of magnitude faster than an instruction level one but the methodology is not valid with a dynamically scheduled superscalar microprocessor.