Design and Implementation of a High Bit Rate HDLC Transceiver Based on a Modified MT8952B Controller
S. Hamed Javadi, Ali Peiravi · AUSTRALIAN JOURNAL OF BASIC AND APPLIED SCIENCES · 2009
To transmit and receive data over any network successfully, a protocol i s re quired to manage t he flow. H igh-level Data Li nk Control (HDLC) protocol is defined in La yer 2 of OSI model and is one of t he most c ommonly use d layer 2 protocols. HDLC supports both fu ll-duplex and half- duplex data transfer. In addition, it offers error control and flow control. Using a modified MT8952B controller design, t he current re search presents a new method for im plementing an ultra high bit rate HDLC Controller that is compatible wi th ST -BUS f ormat using Xilinx Virtex FPGA as the target technology using VHDL f or implementation. The HDLC Transceiver is used to transmit and receive the HDLC frames. Im plementing the HDLC protocol t ransceiver in FPGA offers the flexibility, upgradeability and c ustomization benefits of programmable logic and a lso r educes the total cost of every project wh ich involves H DLC protocol controllers.