Design of an analog CMOS self-learning MLP chip
G. M. Bo, Daniele D. Caviglia, Hussein Chiblè, Maurizio Valle · 2002
In this paper we present the analog CMOS design of a multi-layer-perceptron network with on-chip by-pattern back-propagation learning. The learning algorithm is based on a local learning rate adaptation technique which makes the on-chip implementation more efficient in terms of convergence speed. Circuit simulation results validate the network behavior.