The asynchronous 24MB on-chip level-3 cache for a dual-core Itanium-family processor
John Wuu, Don Weiss, Charles R. Morganti, Michael Dreesen · 2005
The 24MB level-3 cache on a dual-core Itanium/spl reg/ processor has more than 1.47G transistors. The cache uses an asynchronous design to reduce latency and power, and it includes other power saving and reliability improvement features. The 5-cycle array operates above 2GHz at 0.8V and 85/spl deg/C while consuming less than 4.2W.