Implementation of a 4.8 Kbps CELP speech coder on a TMS320C44 processor board
T.T. Teo, E.C. Tan, C.K. Kwoh · 2002
The CELP algorithm has been used in the standardization of the Federal Standard FS-1016 speech codec in 1991. Over the years, much research effort results in many variants of CELP with optimization in the computation time, codebook structures and search strategies. This paper presents the implementation of a 4.8 Kbps code excited linear prediction speech coder using the TMS320C44 digital signal processor. The emphasis is on exploiting the DSP hardware platform.