System level power analysis
M.J. Irwin, Robert Michael Owens, Huzefa Mehta · 1996
This thesis addresses research issues in system level power analysis. In order to evaluate power alternatives in the design space it is necessary to have an efficient tool that allows quick and accurate estimation of power dissipation. This tool should provide the right environment to highlight energy consumers in the chip and can help computer architects to design low power processors, compiler writers to re-target code for low-power, and application developers to compare the power consumption of various algorithms and data structures. A reasonably accurate high level power estimation tool has been developed which can assist system designers in analyzing power consumption during early stages of the design. This tool operates on the paradigm of simulation and profiling and accepts as input stimuli, instructions of a program and data and outputs, statistics on modules and instructions using pre-characterized energy tables of macro modules. Micro-instruction analysis is used to model the instruction and the overall accuracy per instruction is within 8% of IRSIM-CAP, while being orders of magnitude faster. Simulation tools at the system level however require accurate and efficient modeling of various underlying hardware macros. Using the average energy value of the macro module during simulation can incur large errors on power consumption. On the other extreme, fully characterized table based energy models of modules can capture the data dependence effects, however the size of the table grows rapidly with the increase in input size. A novel modeling method is developed which clusters the energy transition table under the user defined error (average, RMS, maximum) and coverage sufficiency criterion, reducing the number of table entries. This characterization is only required once for each module. During simulation, energy expenditure is obtained by looking up the energy table using the transition vector. The DLX simulator is instrumented to account for energy consumption. Programs can be compiled for this machine and evaluated on the instrumented simulator. Effects of different software alternatives such as loop unrolling, software pipelining and recursion elimination and of different algorithms and benchmarks on power and energy consumption are studied using this tool. A novel compiler level optimization is proposed which reduces the switching activity in the register file decoder and instruction register during the post code generation phase by doing smart register encoding. There is no hardware penalty since this is purely a compiler optimization. Results on some benchmarks show that the energy consumption of the DLX processor can be reduced by 9.82% maximum and 4.25% average.