A 640 MB/s bi-directional data strobed, double-data-rate SDRAM with a 40 mW DLL circuit for a 256 MB memory system
C. Kim, S. Cho, Jin‐Woo Lee, BongSoo Kim, Chang Hyun Park, S. Lee, Jeongjin Roh, Hyoungsik Nam, Dae-Hyun Kim, Tae‐Sung Jung · 1998
In a memory system employing wide channel high-performance DRAMs, skews resulting from nonideal system and chip environments become the most critical factor. This 256 MB memory system achieves 256 Gb/s peak bandwidth with a 160 MHz clock and 64b channel using a /spl plusmn/0.4 V-swing, push-pull type I/O interface (SSTL).