Implementation of Low Area and High Data Throughput CRC Design on FPGA
Hesham F. A. Hamed, F.A. Elmisery, Ahmed A. H. A. Elkader · International journal of advanced research in computer science and electronics engineering · 2012
This paper introduces an alternative way to implement CRC hardware on FPGA to speed up the CRC calculation while maintaining a verylow area. The traditional implementations with high data throughput have very large area. In Ourdesign weused the CRC Reduced Table Lookup Algorithm (RTLA) for achieving very low area, while using pipelined architecture for having high data throughput.In our implementation we have reached a data throughput of more than 100 Gbps when the data input width is 200 bits or more, and relatively fixed maximum frequency which make doubling the data width approximately doubles the data throughput. The proposed design will be suitable candidate for manycommunication protocols such as 100 Gbps Ethernet.