Scan test in 18×18 bits Booth coding-Wallace tree multiplier
Wang Dong-Hui, Ruan Jie, Li Yungang, Chaohuan Hou · 2002
Scan test can be inserted around hard IP cores that have not been designed with DFT approaches. An 18/spl times/18 bits Booth coding-Wallace tree multiplier has been designed with full custom approach with 0.6 /spl mu/m CMOS technology. When we reuse the multiplier in another chip, scan chain has been inserted around it to increase the fault coverage. After scan insertion, the multiplier needs 4.7% more area and 24.4% more delay time, while the fault coverage reaches 95%.