High-level synthesis of digital circuits using global scheduling and binding algorithms.
Pierre G. Paulin · 1988
The need to rapidly produce designs of digital integrated circuits has motivated the development of high-level synthesis tools that automatically generate a design of a digital system from an abstract specification of its behavior. This dissertation describes a multi-paradigm implementation of a high-level synthesis tool that features: (1) A new global force-directed scheduling algorithm that attempts to balance the distribution of operations that make use of the same hardware resources; therefore minimizing functional unit, register and interconnection costs. (2) A rule-based expert allocater that performs a global analysis of the control and data flow graph and uses heuristic rules to preselect hardware modules based on a speed constraint. (3) A stepwise refinement approach to scheduling and allocation where preliminary allocation information is used to guide and optimize the scheduling process. (4) Data path synthesis algorithms that attempt to minimize interconnect at all stages of the synthesis process.