A framework for testing stuck-open fault in CMOS LSI/VLSI circuits
Eltayeb Salih Abuelyaman, N.E. Hedroug · 2003
A conceptual framework for modeling of CMOS stuck-open faults by classical stuck-at faults is presented. Stuck-open faults can be mapped one-to-one onto stuck-at faults for a gate level, clock-mode fault simulation. The disadvantage of this modeling is that it restricts the circuit layout to logic gates, and hence an increase in chip area is expected. Such an increase is acceptable when the modeling reduces the staggering fault simulation time by a large factor.>