Direct FPGA-based power profiling for a RISC processor
Cosmin Cernăzanu-Glăvan, Marius Marcu, Alexandru Amaricăi, Stefan Fedeac, Madalin Ghenea, Zheng Wang, Anupam Chattopadhyay, Jan Henrik Weinstock, Rainer Leupers · 2015
This paper investigates the possibility of creating an energy profile of a RISC processor instruction set in the prototyping phase, using FPGA implementation and physical measurements. In order to determine the power consumption at instruction-level, several programs have been developed and run on the processor implementation on FPGA. The experiments have focused at the following groups of instructions: arithmetic and logic (ALU) instructions, memory access instructions, control instructions, compare and move instructions. The main goal of our work is the investigation of the correlation between dynamic power consumption of a RISC processor design implemented in different technologies (FPGA vs. ASIC) and manufacturing processes, called power technology gap. The achieved correlation coefficient between the FPGA 45nm physical power measurements and ASIC 45nm power estimation is 86.39%.