Parallelizing SHA-256, SHA-1 and MD5 and AES on the Cell Broadband Engine
George W. Dinolt, David Canright, B. Allen, Simson Garfinkel · 2010
The Cell BE Architecture connects a Power processor with several synergistic processing units via a high-speed bus, allowing parallel processing on a chip. Architectural features enabling high speed performance include SIMD, many wide registers, DMA provisions, and dual-issue instructions. We have developed extraordinarily high performance implementatioins of SHA-256, SHA-1 and MD5 for this architecture. We have also developed parallelized implementations of AES Encryption.