A VLSI CMOS circuit design technique to aid test generation
Dick L. Liu, Edward J. McCluskey · Defense Technical Information Center (DTIC) · 1986
This paper describes a new design technique for fully-testable CMOS combinational circuits and a 3-pattern test scheme to detect switch-level (stuck-open and stuck-on) faults. A fully-testable combinational circuit is implemented with specially designed gates that have no undetectable stuck-on faults. Switch-level faults in this type of combinational circuit can be detected with a 3-pattern test scheme. These 3-pattern tests are easy to generate with a gate-level automatic test pattern generator (ATPG) that offers better performance than a switch-level ATPG.