Simulation-based sequential equivalence checking of RTL VHDL
Fulvio Corno, Matteo Sonza Reorda, Giovanni Squillero · 2003
This paper presents a novel approach to equivalence verification of RT-level descriptions. The proposed approach sacrifices exactness in favor of applicability: it is not always able to produce an answer, but it is able to check sequential equivalence of large systems. Furthermore, being based on commercial VHDL tools, it does not have arbitrary limitations in the syntax of the descriptions.