UltraSPARC-III: a 3rd generation 64 b SPARC microprocessor
Gary Lauterbach, D. Greenley, Sameer Ahmed, M. Boffey, Joseph I. Chamdani, Si-En Chang, D. Chen, Yu Fang, K. Holdbrook, M. Hsieh, B. Keish, R. Melanson, C. Narasimhaiah, Joseph Petolino, Tung Pham, L. Quach, Kit Tam, Duong Tong, Liuxi Yang, K.H.K. Yau · 2002
UltraSPARC-III (US-III) is a 64 b 800 MHz 4-instruction-issue superscalar microprocessor for high-performance desktop workstation, work group server, and enterprise server platforms. On-chip caches include a 64 kB 4-way associative for data, 32 kB 4-way associative for instructions, a 2 k B 4-way associative data prefetch cache, and a 2 kB 4-way associative write. A 90 kB on-chip tag array supports the off-chip 8 MB unified second-level cache. The 23 M-transistor chip in a 0.15 /spl mu/m, 7-layer metal process consumes 60 W from a 1.5 V supply.