On the prediction of fault behavior based on workload
E.W. Czeck · 1991
With computer applications requiring extreme dependability, their design mandates the ability to operate in the presence of faults. The problem of assuring that the design goals are achieved requires the characterization of behavior under the expected faulty conditions. However, injection of faults is difficult due to the complexity and level of integration of contemporary VLSI implementations. Models for predicting fault behavior need to be developed and validated based on the manifestation of low-level faults. This thesis explores the effects of gate-level faults on system operation as a basis for fault behavior models at the program level. A simulation model of the IBM RT PC, capable of executing actual application code, was developed. Gate-level transient faults, selected since their behavior closely resembles actual faults, were injected at several locations (sites). Additionally, multiple applications were executed, with faults injected across their execution time, to observe the dependencies of workload. Several prediction models for fault manifestation were developed based on the instruction executing at the injection time and the location of the fault. The models were developed based on the behavior of one workload and evaluated with data from the other workloads. The models showed that behavior is dependent more on the workload structure (sequencing) rather than the instruction mix of the workload. Overall, the expected prediction coverage for the models range from 60% to 80% for the locations, workloads, and processor model studied. Fault manifestations were observed at the program level to demonstrate that gate-level fault effects can emulated through software-implemented fault injection (SWIFI). This observation, coupled with an analysis of the simulation model, shows that a subset of faults within all sub-components are capable of being emulated by SWIFI. Overall, the use of SWIFI, coupled with the prediction models, showed a factor of eight reduction-of-effort for fault injection studies over an equivalent simulation study. In summary, these results aid in understanding the effects of transient gate-level faults on program behavior and allow for further generation and validation of new fault models, fault injection methods, and error detection mechanisms.