VLSI implementation of a new bit-level pipelined architecture for 2-D allpass digital filters
D. Alam, S.S. Lawson · 2002
A new bit-level pipelined architecture for a 2-D 2nd/spl times/2nd order allpass digital filter is presented. The minimum multiplier architecture with octagonal symmetry results in only 5 filter coefficients. The filter is capable of processing signals of size 64/spl times/64. The critical path of the word level architecture is T/sub m/+3T/sub a/, whilst the bit-level pipelined architecture has a critical path which is approximately 2/3 of this. Moreover the clock rate of the filter is equivalent to its sample rate and is typically 34 MHz. The architecture has been modelled in a standard cell 1 /spl mu/m CMOS process, and the die size is 5.7 mm/spl times/6.9 mm.