A Gentle Introduction to System Verification
Love Ekenberg · New Trends in Software Methodologies, Tools and Techniques · 2005
Verification is an important instrument in the analysis of systems. Roughly, this means that requirements and designs are analyzed formally to determine their relationships. Various candidates for formalizing system development and integration have been proposed. However, a major obstacle is that these introduce non-standard objects and formalisms, leading to severe confusion. This is because these models often are unnecessarily complicated with several disadvantages regarding semantics as well as complexity. While avoiding the mathematical details as far as possible, we present some basic verification ideas using a simple language such as predicate logic and demonstrate how this can be used for defining and analyzing static and dynamic requirement fulfillment by designs as well as for detecting conflicts. The formalities can be found in the appendix.