A 16M Bit 125MHz Cached DRAM
Dennis Blankenship, Bill Randolph, Hiroyuki Fukuda, D. Tommy King, Mohammad Taghavi, Tomonori Doguchi, Rhonda Cassada, Melvin Isom, Robert A. Walker, Tim Lao, Steve Mann · European Solid-State Circuits Conference · 1995
The Cached DRAM (CDRAM) is a synchronous memory device that can deliver I/O bandwidth and performance necessary for today's high-speed computer systems. Independent address and control circuitry for the integrated DRAM and SRAM give the CDRAM the same flexibility as an L2 caching system with much lower cost and power usage. An internal 128 bit data bus enables the CDRAM to utilize a small SRAM cache and still obtain high cache hit rates. The smaller cache has the dual benefits of reducing chip cost and producing faster cache access times. Finally, the CDRAM supports LVTTL (Low Voltage TTL) I/O interfaces and burst mode operations, thus making it easily adaptable to most computer systems.