1.4ns Gate Arrays with Configurable RAM and High Testability
H. Nakazato, R. Ikeda, Shohei Yamada, T. Sano, Tadayuki Ogawa, Y. Nishimura, Y. Marui · 1986
Two gate arrays, 10k gates with 4.6k bit SRAM and 9k gates with 9.2k bit SRAM, have been developed using 1.5μm rule CMOS technology and two layer metallization. They have realized 1.4ns gate delay (2 input NAND, F/0=3, l=3mm) and 18ns address access time. High testability by scan path technique, RAM data throughput mode and automatic test data generation, and efficient logic design by neat CAD support tools have been achieved. Words × bits of built-in RAM are configurable by metallization. A fully asynchronous static RAM with address transition detector eliminates cumbersome timing problems, such as clock skew. The gate arrays are applicable for small to medium size data processing systems.