Efficient test generation for CMOS circuits
Damu Radhakrishnan, CONGMIN LAI · 2002
A new concept, path testing, is introduced. This approach leads to the simultaneous testing of a set of MOS transistors in a path of a CMOS circuit instead of individual ones. Using this concept, the authors generate a Karnaugh map procedure to identify a minimal robust test set for a direct CMOS complementary gate. The test set derived is implementation independent, and it can be used for detecting both single and multiple faults.>