Fast Learning Algorithms for Self-Organizing Map Employing Rough Comparison WTA and its Digital Hardware Implementation
Hakaru Tamukoh, Keiichi Horio, Takeshi Yamakawa · IEICE Transactions on Electronics · 2004
This paper describes a new fast learning algorithm for Self-Organizing Map employing a rough comparison winner-take-all and its digital hardware architecture. In rough comparison winner-take-all algorithm, the winner unit is roughly and strictly assigned in early and later learning stage, respectively. It realizes both of high accuracy and fast learning. The digital hardware of the self-organizing map with proposed WTA algorithm is implemented using FPGA. Experimental results show that the designed hardware is superior to other hardware with respect to calculation speed.