Design and evaluation of the high performance multi-processor server
Masaki Suimye Morioka, K. Kurosawa, Seiji Miura, Tetsuaki Nakamikawa, S. Ishikawa · 2002
The paper discusses the architecture and performance of a prototype RISC multi-processor server designed for a business system like OLTP (online transaction processing). The combination of a low-latency cache-to-cache copy and an 8-way highly interleaved main memory realize high performance for the OLTP program. We analyzed the activity of the multi-processor system when executing the OLTP program by using the trace-driven simulator including kernel execution. The main findings are that: cache misses due to task migration and ping-ponging of kernel shared data occupy a larger part of the total misses, especially in a large cache capacity because of intensive I/O activities; and the low-latency cache-to-cache copy is very effective because 50-60% of the data read accesses are supplied by the cache-to-cache copy in a large cache capacity.>