Rapid design of complex DSP cores
John V McCanny, David Trainor, Yi Hu, Tiong Jiu Ding · Research Portal (Queen's University Belfast) · 1997
Methods are presented for the rapid design of Digital Signal Processing chips which are based on the use of hierarchical VHDL libraries. These capture advanced, parameterised DSP architectures (silicon intellectual property) at various levels of complexity. Resulting designs can be implemented in ASIC, PLD and FPGA technologies and are portable across many silicon foundries. Complex DSP designs are developed in a fraction of the time normally required and results compete very favourably with conventional methods. The approach is illustrated through its application to the design of FFT, DCT and Reed Solomon processors.