Operating System Design for Partiallly Reconfigurable Logic Devices
Herbert Walder · Repository for Publications and Research Data (ETH Zurich) · 2005
The logic capacity of current SRAM-based FPGAs (Field Programmable Gate Arrays) amounts to multiple times the size of coarse-grained circuits, such as AR-filters, spectral transformations (FFTs, DCTs), and crypto-or multimedia codees.Furthermore, modem FPGAs are partially reconfigurable; i.e., parts of the FPGA area can be altered during run-time, while other parts not involved in the reconfiguration process continue to operate in parallel.These characteristics allow for novel use ofFPGAs as subcomponents in embedded systems: Several independent logic circuits (so-called hardware tasks) can be loaded, executed, and removed again after completion, whereas subsequent hardware tasks can reuse the same resources.Due to these properties, an FPGA becomes a dynamically allocatable resource.In this dissertation, a novel kind of operating system, a Reconfigurable Hardware Operating System (RHWOS) is proposed that meets thefollowing requirements: