Cyclic convolutions using low complexity dedicated hardware
Nåahåid Raòhmåan · 2006
Cyclic Convolution plays a central role in digital signal processing. This thesis develops an architecture to compute cyclic convolution of l\' = 2 points for arbitrary 1/. We de\'elop and use a bilinear algorithm as the basis of the hardware platform. The architecture and its control was simulated using v.mn and sy'nthesized a.'i an Application specific Integrated Circuit (ASIC) using Mentor Graphics tools. This provided us with the time and hard ware complexity' of the archi tect ure. The Hardware complexity of our architecture is independant of the convolution size as compared to the complexity of a memoryless implement at ion. However. the time complexity' of our architecture is O(N 15S ). Thus this architecture will be ideal in situations where 10\\' hardware complexity is more important than speed.