An optimal IEEE 1500 core wrapper design for improved test access and reduced test time
Brendan Mullane, M. Higgins, Ciaran MacNamee · 2008
IEEE 1500 test wrappers that enable higher test bandwidth capability, system bus connectivity and efficient test vector organization are presented. Embedded core wrappers and test vectors that seamlessly work with ASIC and FPGA design flows are illustrated. Implementation and test-chip design show the positive impact on test time with potential for minimal wiring and logic overhead savings.