Synthesis for Testability: Binary Decision Diagrams
Bernd Becker · Teubner-Texte zur Informatik · 1992
We investigate the testability properties of Boolean circuits derived from (Reduced Ordered) Binary Decision Diagrams. It is shown that BDD-cirucits (or at least) BDD-like circuits are easily testable with respect to different fault models (cellular, stuck-at and path delay fault model). Furthermore the circuits and the test sets can be constructed efficiently.