Yield enhancement through fast statistical scan test analysis for digital logic
Hans‐Peter Erb, Christian Burmer, Andreas Leininger · 2005
To enable fast technology ramp up and stable high yield a good understanding and fast detection of yield detractors is required. This paper focuses on fast statistical analysis of failures in the logic circuit part of SOC's, especially during ramp-up of a new product or technology. The failing chips response to the production test program is the key for a statistical search for systematic yield losses. The scan test method allows diagnosing the failing circuit nodes in the logic based on the chips misbehavior. Intelligent processing and analysis of this information enables identification of important yield detractors. A description of the approach and experimental results are provided