Analysis of a Test Method for Delay Faults in NoC Interconnects
Tomas Bengtsson, Artur Jutman, Shashi Bhusan Kumar, Raimund Ubar, Zebo Peng · 2006
Testing of delay faults in chips built using submicron technology and working at very high speed can only be done using an at-speed testing technique. Such a method has been proposed for testing of delay faults in links connecting two switches which operate asynchronously with respect to each other in a NoC. In this paper, we present a detailed analytical analysis about the efficiency of this method. Our analysis shows that the number of tests required for labeling a chip delay-fault free or faulty can be infinity in the worst case. In this method, a chip which can not be labeled fault free is rejected. Our analysis points out to a practical way to trade-off test time with test accuracy. 1.