A 768 k embedded DRAM for 1.244 Gb/s ATM switch in a 0.8 μm logic process
Peter Gillingham, B. Hold, I. Mes, C. O'Connell, P. Schofield, K. Skjaveland, Randy Torrance, T. Wojcicki, Hungkei Keith Chow · 2002
This 256 k DRAM macrocell in a 0.8 /spl mu/m single-poly, double-metal, p-substrate, n-well logic process offers 3 times the density of an embedded SRAM without special processing steps. Robust data retention and soft-error performance are achieved by use of a p-channel 1T cell featuring a flexible high-bandwidth interface to support a variety of applications. Three macrocells are used for a 768 k queue memory in a 1.244 Gb/s ATM switch ASIC.