A 51mW 1.6GHz on-chip network for low-power heterogeneous SoC platform
Kangmin Lee, Se-Joong Lee, Sung-Eun Kim, Hyemi Choi, Dong‐Hyun Kim, Sunyoung Kim, Min-Wuk Lee, Hoi‐Jun Yoo · 2004
A 1.6GHz on-chip network integrating two processors, memories, and an FPGA provides 11.2GB/s bandwidth in 0.18/spl mu/m 6M CMOS technology. The 2-level hierarchical star-connected network using serialized low-energy transmission coding, crossbar partial activation and lowswing signaling dissipates 51 mW at 1.6V supporting globally asynchronous, locally synchronous mode and programmable clocking.