A voice activity detection system based on FPGA
Junhee Jung, Seunghun Jin, Dongkyun Kim, Hyung Soon Kim, Jong Suk Choi, Jae Wook Jeon · 2010
In this paper, we present a FPGA-based voice activity detection system. DoV (Degree of Voicing) and QSNR (Quantile Signal-to-Noise Ratio) are used as parameters of the VAD algorithm of the proposed system. All VAD system functions are implemented using a dedicated parallel architecture, including signal capturing, DoV processing module and QSNR processing module. The system uses several DPRAMs (Dual Port RAMs) inside the FPGA as parallel buffers in which speech data and the intermediate result are stored, to speed up processing. The functional modules process data in parallel using those buffers. The sampling rate of the proposed system is 16 KHz, and the resolution of each sample is 16 bits. The system can generate the VAD result every 15 ms. The proposed system can be used in speech processing such as speech coding and speech recognition.