Design and implementation of a parallel automatic test pattern generation algorithm with low test vector count
Ralph M. Butler, Brion Keller, Srajan Paliwal, Randall M. Schoonover, Joe Swenton · 2002
We present an implementation for parallel ATPG that is constructed so as to achieve a test vector count comparable to the serial algorithm. This task posed a challenge since, unlike previous published works, substantial effort is applied in the serial algorithm to keep the test vector count low. Results on industrial circuits that range in size from 700000 gates to about 3 million gates are presented. Previous works have published results for smaller circuits.